Advanced Verification Engineer

King Global Enterprise Solutions
Published
June 24, 2023
Expires
Never
Location
Linthicum Heights, MD
Job Type

Description

Advanced Verification Engineer

Linthicum Heights, MD, USA

12 month contract

$50-75 hr pay range

Company Description

King Global Enterprise Solutions (KGES) is supporting The United States Solutions Group (USG 1) which provides top talent and technology solutions to government agencies where we aim to make a meaningful difference and add value to the mission. We look for candidates who want to make a difference to their team and its objectives, and in return, we will support you and help you in your goals and career journey.

Job Description

USG 1, supported by KGES, is seeking multiple talented Advanced Verification Engineers for our direct client, a large federal contractor in Linthicum Heights, MD, to join a team of highly qualified, diverse individuals in Digital Technology.

Qualified applicants will become part of the Digital Technology department, which specializes in product designs for a variety of applications from undersea to outer space.

The individuals will perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and System Verilog and Cadence Xcelium simulation tool. This task includes but is not limited to the development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation, etc.

This candidate will have the ability to operate in a team environment and collaborate across different teams as required to accomplish the goals.

Qualifications

  • Work is 100% on site - no remote work available.

Basic Qualifications:

  • Bachelor’s degree (Master’s preferred) in Electrical Engineering or a comparable engineering discipline • 9+ years of design verification experience • Expertise in HDL (VHDL/Verilog) and HVL (System Verilog) • Experience with System Verilog Assertions (SVA) • Advanced knowledge of UVM and System Verilog • Experience with a coverage-driven verification methodology from planning through closure • Knowledge of industry-standard interfaces • Experience with object-oriented programming languages and concepts • Be able to work in teams and communicate clearly across various levels of engineers • Proficiency in scripting languages such as Tcl, Python, or Perl • U.S. citizenship is required for all positions
  • Working a 9/80 schedule is optional.
  • Work is 100% on site - no remote work available.

Additional Information Work is on-site. Remote work is not possible for this position. This position is for our direct client, a large federal contractor. U.S. citizenship is required W2 Only, no 3rd party corp to corp engagement All your information will be kept confidential according to EEO guidelines.

 

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